//__________________________________________________________________
//
//  Module      :   ASYN_FIFO
//              
//  By          :   Kejie
//  E-mail      :   Kejie1208@126.com
//  Created     :   08/12/10 
//  Read Mode   :   First-Word Fall-Through
//                  All Outputs are Registed
//  First-Word
//  Fall-Through
//  Notes:          The First Word into the fifo will be valid in the w_data,
//                  while the r_empty is fall down.
//                  And if r_re is assigned some time, 
//                  then in the next Cycle 
//                  the w_data will be the Second Word  
//___________________________________________________________________

`timescale 1ns/1ns

module  asyn_fifo_nw256_nb291 #(
parameter   L=8,        //Fifo Depth = 2^L+2;
parameter   DW=291        //Data Width = DW;
)
(
   
  input  wire             clka,
  input  wire             clkb,
  input  wire             clr,
  input  wire [11:0]      ram_dp_cfg_register,
  input  wire [DW-1:0]    w_data,
  input  wire             w_we,
  output wire             w_full,
  output wire             w_afull,
            
  output wire [DW-1:0]    r_data,
  input  wire             r_re,
  output wire             r_empty,
  output wire             r_aempty
);
wire            rst_n         ;
wire [L-1:0]    ram_rd_addr   ;
wire [L-1:0]    ram_wr_addr   ;
// wire [L-1:0]    ram_wr_addr_DL;
wire            ram_we_n      ;

assign rst_n = clr;

    DW_fifoctl_s2_sf #(
      .depth(256), 
      .push_ae_lvl(2),
      .push_af_lvl(2),
      .pop_ae_lvl(2),
      .pop_af_lvl(2),
      .err_mode(0), 
      .rst_mode(0),
      .push_sync(2),
      .pop_sync(2),
      .tst_mode(0)
      ) 
    FIFO_CTL(
      .clk_push(clka),
      .clk_pop(clkb),
      .rst_n(rst_n),
      .push_req_n(~w_we),
      .pop_req_n(~r_re),
      .we_n(ram_we_n),
      .push_empty(),
      .push_ae(),
      .push_hf(),
      .push_af(w_afull),
      .push_full(w_full),
      .push_error(),
      .pop_empty(r_empty),
      .pop_ae(),
      .pop_hf(),
      .pop_af(),
      .pop_full(),
      .pop_error(),
      .wr_addr(ram_wr_addr),
      .rd_addr(ram_rd_addr),
      .push_word_count(),
      .pop_word_count(),
      .test(1'b0)
      );
// assign ram_rd_addr_DL = (!pop_req_n) ? ram_rd_addr + 'd1 : ram_rd_addr;



ram_dp_d256_w291_wrapper U_ram_dp_d256_w291_wrapper(
  .clka(clka),
  .clkb(clkb),
  .ram_dp_cfg_register(ram_dp_cfg_register),
  //we write enable,write,active high
  .wea(~ram_we_n),
  .web(1'b0),
  .addra(ram_wr_addr),
  .addrb(ram_rd_addr),
  .dina(w_data),
  .dinb(291'b0),
  .douta(),
  .doutb(r_data)
  );

endmodule  

